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pd720122 mos integrated circuit data sheet usb2.0 generic device controller document no. s16685ej2v0ds00 (2nd edition) date published june 2003 ns cp (k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. 2003 the mark shows major revised points. the pd720122 is usb2.0 generic device controller, which combines the nec electronics usb2.0 phy and end- point controller. the controller has certified by usb implementers forum. end-point controller has banked two bulk end- point and one interrupt end-point, and selectable three general cpu bus-types, suitable for designing various usb device. the controller has the external local bus, that enables to perform high speed data transferring when cpu is accessing to the controller. these ip blocks in the controller are based completely on an nec electronics asic core, so pd720122 is suitable to design for the prototype system that are intended to design asic in the future. detailed function descriptions are provided in the following user?s manual. be sure to read the manual before designing. pd720122 user?s manual: s15829e features ? complaint with usb2.0 specification (maximum data transferring rate: 480 mbps) usb2.0 certified (testid=40000822) high(480mbps) / full(12mbps)- speed support and switch automatically easy to design nec electronics asic generic usb2.0 device controller two bulk end-points and one interrupt end-point performed data local bus independent from cpu bus. (maximum data transferring rate: 21 mbps with dma mode ) selectable three cpu bus interface ordering information part number package pd720122gc-9eu 100-pin plastic tqfp (fine pitch) (14 14) pd720122f1-dn2 109-pin plastic fbga (11 11)
data sheet s16685ej2v0ds 2 pd720122 block diagram phy core : usb2.0 transceiver with serial interface engine epc2 core : endpoint controller biu core : bus interface unit biu core epc2 core phy core ep1 bulkout 512 byte x2 ep3 interrupt in 8 byte ep2 bulkin 512 byte x2 ep0 control in 64 byte protocol controller cpu bus local bus usb bus ep0 control out 64 byte
data sheet s16685ej2v0ds 3 pd720122 pin configuration 100-pin plastic tqfp (fine pitch) (14 14) pd720122gc-9eu top view remark the function of the pin is shown with function 1/function 2/function 3 from the left.
data sheet s16685ej2v0ds 4 pd720122 pd720122gc-9eu (1/2) pin no. pin name function1 pin name function2 pin name function3 pin no. pin name function1 pin name function2 pin name function3 1v dd v dd v dd 26 gnd gnd gnd 2 resetb resetb resetb 27 d8 reserved d8 3 gnd gnd gnd 28 d9 reserved d9 4 xin_clk xin_clk xin_clk 29 d10 reserved d10 5 xout xout xout 30 d11 reserved d11 6 gnd gnd gnd 31 d12 reserved d12 7 csb csb csb 32 d13 reserved d13 8 intb_all ale ale 33 d14 reserved d14 9 a1 intb_all intb_all 34 d15 reserved d15 10 a2 reserved reserved 35 v dd v dd v dd 11 a3 reserved reserved 36 gnd gnd gnd 12 a4 reserved reserved 37 wrb wrb wrb 13 a5 reserved reserved 38 rdb rdb rdb 14 a6 reserved reserved 39 int0b int0b int0b 15 a7 reserved reserved 40 int1b int1b int1b 16 gnd gnd gnd 41 int2b int2b int2b 17 d0 ad0 d0 42 active active active 18 d1 ad1 ad1 43 scan1 scan1 scan1 19 d2 ad2 ad2 44 scan0 scan0 scan0 20 d3 ad3 ad3 45 m2 m2 m2 21 d4 ad4 ad4 46 ep1_drqb ep1_drqb ep1_drqb 22 d5 ad5 ad5 47 ep1_dackb ep1_dackb ep1_dackb 23 d6 ad6 ad6 48 ep1_rdb ep1_rdb reserved 24 d7 ad7 ad7 49 ep1_tcb ep1_tcb ep1_tcb 25 v dd v dd v dd 50 gnd gnd gnd
data sheet s16685ej2v0ds 5 pd720122 pd720122gc-9eu (2/2) pin no. pin name fucntion1 pin name function2 pin name function3 pin no. pin name fucntion1 pin name function2 pin name function3 51 v dd v dd v dd 76 gnd gnd gnd 52 fm21 fm21 fm21 77 bunri bunri bunri 53 ep2_drqb ep2_drqb ep2_drqb 78 rref rref rref 54 ep2_dackb ep2_dackb ep2_dackb 79 av ss (r) av ss (r) av ss (r) 55 ep2_wrb ep2_wrb reserved 80 av dd av dd av dd 56 ep2_tcb ep2_tcb ep2_tcb 81 av ss av ss av ss 57 ld0 ld0 reserved 82 rpu rpu rpu 58 ld1 ld1 reserved 83 v ss v ss v ss 59 ld2 ld2 reserved 84 rsdp rsdp rsdp 60 ld3 ld3 reserved 85 dp dp dp 61 gnd gnd gnd 86 v dd v dd v dd 62 ld4 ld4 reserved 87 dm dm dm 63 ld5 ld5 reserved 88 rsdm rsdm rsdm 64 ld6 ld6 reserved 89 v ss v ss v ss 65 ld7 ld7 reserved 90 nc nc nc 66 ld8 ld8 reserved 91 pv ss pv ss pv ss 67 ld9 ld9 reserved 92 nc nc nc 68 gnd gnd gnd 93 pv dd pv dd pv dd 69 ld10 ld10 reserved 94 v ss v ss v ss 70 ld11 ld11 reserved 95 v dd v dd v dd 71 ld12 ld12 reserved 96 v ss v ss v ss 72 ld13 ld13 reserved 97 m1 m1 m1 73 ld14 ld14 reserved 98 m0 m0 m0 74 ld15 ld15 reserved 99 vbus vbus vbus 75 v dd v dd v dd 100 gnd gnd gnd remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 9.1 k ? .
data sheet s16685ej2v0ds 6 pd720122 109-pin plastic fbga (11 11) pd720122f1-dn2 bottom view remarks the pin name is showing it with function1. as for the pin name of function2 and function3, please refer to the table of the next page.
data sheet s16685ej2v0ds 7 pd720122 pd720122f1-dn2 (1/2) pin no. pin name function1 pin name function2 pin name function3 pin no. pin name function1 pin name function2 pin name function3 1nc nc nc26 av ss av ss av ss 2 d8 reserved d8 27 rsdp rsdp rsdp 3 d10 reserved d10 28 v dd v dd v dd 4 d12 reserved d12 29 nc nc nc 5 d15 reserved d15 30 nc nc nc 6 gnd gnd gnd 31 v dd v dd v dd 7 int1b int1b int1b 32 m1 m1 m1 8 active active active 33 vbus vbus vbus 9m2 m2 m234 nc nc nc 10 ep1_dackb ep1_dackb ep1_dackb 35 resetb resetb resetb 11 ep1_tcb ep1_tcb ep1_tcb 36 xin_clk xin_clk xin_clk 12 nc nc nc 37 gnd gnd gnd 13 fm21 fm21 fm21 38 a1 intb_all intb_all 14 ep2_dackb ep2_dackb ep2_dackb 39 a3 reserved reserved 15 ep2_tcb ep2_tcb ep2_tcb 40 a7 reserved reserved 16 ld2 ld2 reserved 41 d0 ad0 d0 17 gnd gnd gnd 42 d3 ad3 ad3 18 ld7 ld7 reserved 43 d5 ad5 ad5 19 ld9 ld9 reserved 44 d7 ad7 ad7 20 ld11 ld11 reserved 45 nc nc nc 21 ld13 ld13 reserved 46 d9 reserved d9 22 ld15 ld15 reserved 47 d11 reserved d11 23 nc nc nc 48 d14 reserved d14 24 bunri bunri bunri 49 rdb rdb rdb 25 av ss (r) av ss (r) av ss (r) 50 int2b int2b int2b remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 9.1 k ? .
data sheet s16685ej2v0ds 8 pd720122 pd720122f1-dn2 (2/2) pin no. pin name function1 pin name function2 pin name function3 pin no. pin name function1 pin name function2 pin name function3 51 scan0 scan0 scan0 81 gnd gnd gnd 52 ep1_drqb ep1_drqb ep1_drqb 82 d13 reserved d13 53 ep1_rdb ep1_rdb reserved 83 v dd v dd v dd 54 nc nc nc 84 int0b int0b int0b 55 ep2_drqb ep2_drqb ep2_drqb 85 wrb wrb wrb 56 ep2_wrb ep2_wrb reserved 86 scan1 scan1 scan1 57 ld1 ld1 reserved 87 v dd v dd v dd 58 ld5 ld5 reserved 88 gnd gnd gnd 59 ld8 ld8 reserved 89 ld0 ld0 reserved 60 ld10 ld10 reserved 90 ld3 ld3 reserved 61 ld12 ld12 reserved 91 ld6 ld6 reserved 62 ld14 ld14 reserved 92 ld4 ld4 reserved 63 nc nc nc 93 gnd gnd gnd 64 rref rref rref 94 v dd v dd v dd 65 av dd av dd av dd 95 gnd gnd gnd 66 gnd gnd gnd 96 rpu rpu rpu 67 rsdm rsdm rsdm 97 dp dp dp 68 pv ss pv ss pv ss 98 gnd gnd gnd 69 gnd gnd gnd 99 dm dm dm 70 gnd gnd gnd 100 pv dd pv dd pv dd 71 m0 m0 m0 101 v dd v dd v dd 72 nc nc nc 102 gnd gnd gnd 73 gnd gnd gnd 103 csb csb csb 74 xout xout xout 104 a2 reserved reserved 75 intb_all ale ale 105 a6 reserved reserved 76 a5 reserved reserved 106 a4 reserved reserved 77 gnd gnd gnd 107 d1 ad1 ad1 78 d2 ad2 ad2 108 v dd v dd v dd 79 d4 ad4 ad4 109 gnd gnd gnd 80 d6 ad6 ad6 - - - -
data sheet s16685ej2v0ds 9 pd720122 1. pin information (1/2) pin name i/o buffer type active level function resetb i 5 v tolerant input schmitt low asynchronous reset signaling xin_clk i 3.3 v input system clock input or oscillator in xout o 3.3 v output oscillator out csb i 5 v tolerant input low chip select signal intb_all o 5 v tolerant output low interrupt request signal ale i 5 v tolerant input high address strobe signal (function2/3) a(7:1) i 5 v tolerant input address input (function1) d(15:0) i/o 5 v tolerant i/o data bus (i/o) (function1) ad(7:0) i/o 5 v tolerant i/o address/data multiplexed bus (i/o) (function2) d0 i/o 5 v tolerant i/o data bus (i/o) (function3) ad(7:1) i/o 5 v tolerant i/o address/data multiplexed bus (i/o) (function3) d(15:8) i/o 5 v tolerant i/o data bus (i/o) (function3) wrb i 5 v tolerant input low write command input rdb i 5 v tolerant input low read command input int0b o 5 v tolerant output low interrupt request (int status 0) int1b o 5 v tolerant output low interrupt request (int status 1) int2b o 5 v tolerant output low interrupt request (int status 2) active i 5 v tolerant input dma-related pins active level select(function2/3) scan(1:0) i 3.3 v input 50 k ? pull down chip test pin. m2 o 5 v tolerant output status output pin ep1_drqb o 5 v tolerant output low dma transfer request output pin of ep1 ep1_dackb i 5 v tolerant input low dma transfer enable input pin of ep1 ep1_rdb i 5 v tolerant input low dma read command input pin of ep1 ep1_tcb i 5 v tolerant input low dma terminal count input pin of ep1 fm21 i 3.3 v input nec electronics test pin ep2_drqb o 5 v tolerant output low dma transfer request output pin of ep2 ep2_dackb i 5 v tolerant input low dma transfer enable input pin of ep2 ep2_wrb i 5 v tolerant input low dma write command input pin of ep2 ep2_tcb i 5 v tolerant input low dma terminal count input pin of ep2 ld(15:0) i/o 5 v tolerant i/o data bus (i/o) pin for external local bus bunri i 5v torelant input nec electronics test pin rref a analog reference resistor rpu a usb pull-up control usb?s 1.5 k ? pull-up resistor control rsdp o usb full speed d+ o usb?s full speed d+ signal dp i/o usb high speed d+ i/o usb?s high speed d+ signal dm i/o usb high speed d- i/o usb?s high speed d ? signal
data sheet s16685ej2v0ds 10 pd720122 (2/2) pin name i/o buffer type active level function rsdm o usb full speed d- o usb?s full speed d ? signal m(1:0) i 5 v tolerant input function mode setting vbus i 5 v tolerant input note vbus monitoring av dd , pv dd 3.3 v dd for analog circuit v dd 3.3 v dd av ss , pv ss v ss for analog circuit v ss , gnd v ss nc not connect reserved not used note vbus pin may be used to monitor for vbus line even if v dd , av dd , and pv dd are shut off. system must ensure that the input voltage level for vbus pin is less than 3.0 v due to the absolute maximum rating is not exceeded. remark ?5 v tolerant? means that the buffer is 3.3 v buffer with 5 v tolerant circuit. the operation mode of the biu can be set by external pins, as shown below. fix external pins (m1 and m0) when using them. pin m1 m0 biu operation mode outline 0 0 16-bit mode (function 1) a 16-bit cpu bus and an external local bus dedicated to data transfer for bulk in/out can be used in this mode. the internal register length is 16 bits. 0 1 8-bit mode (function 2) multiplexed bus mode of 8-bit address bus and 8-bit data bus. the register length is 8 bits only in this mode (registers can only be accessed in byte units). therefore, the address space in this mode differs from that in the other modes. the active levels of some external local bus control pins can be changed by the active pin. 1 0 16-bit mix mode (function 3) multiplexed bus mode of 8-bit address bus and 16-bit data bus. the internal register length is 16 bits. the active levels of some external local bus control pins can be changed by the active pin. 1 1 setting prohibited (function 4) setting prohibited
data sheet s16685ej2v0ds 11 pd720122 2. electrical specifications 2.1 buffer list 3.3 v oscillator interface xin,xout 3.3 v input buffer fm21,scan(1:0) 5v torelant input buffer resetb,csb,a(7:0),wrb,rdb,active,ep1_dackb,ep1_rdb,ep1_tcb,ep2_dackb,ep2_wrb, ep2_tcb,bunri,m0,m1,vbus,ale 5v torelant output buffer intb_all,int0b,int1b,int2b,m2,ep1_drqb,ep2_drqb 5v torelant i/o buffer d(15:0),ld(15:0),ad(7:0),d0,ad(7:1),d(15:8) usb interface dp,dm,rsdp,rsdm,rref,rpu 2.2 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd indicates voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates absolute tolerance value for dc current to prevent damage or reduced reliability when a current flows out of or into an output pin. operating temperature t a indicates the ambient temperature range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device.
data sheet s16685ej2v0ds 12 pd720122 terms used in recommended operating range parameter symbol meaning power supply voltage v dd indicates the voltage range for normal logic operations occur when v ss = 0 v. high-level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ?max.? value is applied, the input voltage is guaranteed as low level voltage. hysteresys voltage v h indicates the differential between the positive trigger voltage and the negative trigger voltage. input rise time t ri indicates allowable input rise time to input pins. input rise time is transition time from 0.1 v dd to 0.9 v dd . input fall time t fi indicates allowable input fall time to input pins. input fall time is transition time from 0.9 v dd to 0.1 v dd . terms used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. output short circuit current i os indicates the current that flows when the output pin is shorted (to gnd pins) when output is at high-level. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that flows from the output pins when the rated high-level output voltage is being applied.
data sheet s16685ej2v0ds 13 pd720122 2.3 absolute maximum ratings parameter symbol conditions ratings unit voltage v dd ? 0.5 to +4.6 v i/o voltage v i /v o note 1 v i /v o < v dd +3.0 v ? 0.5 to +6.6 v note 2 v i /v o < v dd +0.3 v ? 0.5 to +4.6 v output current i o note 3 i ol = 6 ma 6 ma operating ambient temperature t a 0 to +70 c storage temperature t stg ? 65 to +150 c notes 1. 5 v torelant input buffer, output buffer, i/o buffer 2. 3.3 v input buffer,3.3 v oscillator interface 3. 5 v torelant output buffer, i/o buffer(out) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2.4 recommended operating range parameter symbol conditions min. typ. max. unit power supply voltage v dd 3.3 v power 3.0 3.3 3.6 v negative trigger voltage v n 0.6 1.8 v positive trigger voltage v p 1.2 2.4 v hysteresis voltage v h 0.3 1.5 v input voltage, low v il 00.8v 3.3 v input buffer 2.0 v dd v input voltage, high v ih 5v torelant input buffer, i/o buffer 2.0 5.5 v rise/fall time t r /t f 0 200 ns
data sheet s16685ej2v0ds 14 pd720122 2.5 dc characteristics the dc characteristics are classified into those of the usb interface and those of the biu block. 2.5.1 dc characteristics of usb interface parameter symbol conditions min. max. unit serial resistor between dp (dm) and rsdp (rsdm) r s 35.64 36.36 ? driver output resistance (also serves as high-speed termination) z hsdrv includes r s resistor 40.5 49.5 ? bus pull-up resistor on upstream facing port r pu 1.425 1.575 ? termination voltage for upstream facing port pull-up (full-speed) v term 3.0 3.6 v input levels for full-speed: high-level input voltage (driven) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 low-level input voltage v il 0.8 v differential input sensitivity v di ? (d+) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for full-speed: high-level output voltage v oh r l of 14.25 k ? to v ss 2.8 3.6 v low-level output voltage v ol r l of 1.425 k ? to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch detection threshold (differential signal amplitude) v hssq 100 150 mv high-speed disconnect detection threshold (differential signal amplitude) v hsdsc 525 625 mv high-speed data signaling common mode voltage range (guideline for receiver) v hscm ? 50 500 mv high-speed differential input signaling level see figure 2-4 output levels for high-speed: high-speed idle level v hsoi ? 10.0 10 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10.0 10 mv chirp j level (different voltage) v chirpj 700 1100 mv chirp k level (different voltage) v chirpk ? 900 ? 500 mv
data sheet s16685ej2v0ds 15 pd720122 figure 2-1. differential input sensitivity range for low-/full-speed 4.6 ? 1.0 input voltage range (volts) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 differential output crossover voltage range differential input voltage range figure 2-2. full-speed buffer voh/ioh characteristics for high-speed capable transceiver max min ?0 ?0 ?0 ?0 0 v dd ?.3 vout (v) iout (ma) v dd ?.3 v dd ?.3 v dd ?.8 v dd v dd ?.3 v dd ?.8 v dd ?.8
data sheet s16685ej2v0ds 16 pd720122 figure 2-3. full-speed buffer vol/iol characteristics for high-speed capable transceiver max min 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 vout (v) iout (ma) figure 2-4. receiver sensitivity for transceiver at d+/d ? ? ? ? 0 v differential +400 mv differential 400 mv differential unit interval level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 0% 100%
data sheet s16685ej2v0ds 17 pd720122 figure 2-5. receiver measurement fixtures vbus d+ d- gnd 15.8 ? + to 50- ? input of a high-speed differential oscilloscope, or 50- ? outputs of a high-speed differential data generator 50- ? coax 50- ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s16685ej2v0ds 18 pd720122 2.5.2 dc characteristics of biu parameter symbol conditions min. typ. max. unit off-state output current i oz v o = v dd or gnd 10 a output short current i os ? 250 ma input leakage current i i v i = v dd or gnd 10 ? 5 a output current, low i ol v ol = 0.4 v note 6ma output current, high i oh v oh = 2.4 v ? 2 ma output voltage, low v ol i ol = 0 ma 0.1 v output voltage, high v oh i oh = 0 ma v dd ? 0.2 v note 5v-tolerant output
data sheet s16685ej2v0ds 19 pd720122 2.5.3 pin capacitance parameter symbol conditions min. typ. max. unit input capacitance c in 4.5 6.5 pf output/bidirectional capacitance c out 8.5 11 pf remark these are just estimated values. 2.5.4 power consumption parameter symbol conditions min. typ. max. unit v dd 195 273 ma p h hs mode av dd 12 17 ma v dd 120 168 ma p f fs mode av dd 12 17 ma v dd 1.5 2.2 ma p s1 suspend mode 1 note 1 av dd 0.1 0.2 a v dd 370 520 a power consumption p s2 suspend mode 2 note 2 av dd 0.1 0.2 a notes 1. snd phy reg. spnd bit = 1 2. snd phy reg. spnd bit = 1 gpr reg. connectb bit = 0 gpr reg. pue bit = 0 biu control 0 reg. osc_disconb bit = 1
data sheet s16685ej2v0ds 20 pd720122 2.6 ac characteristics (t a = 0 to +70 c, v dd = 3.3 v 10%) the ac characteristics are classified into those of the usb interface block and those of the biu. 2.6.1 overall ac characteristics and those of biu (1) clock parameter symbol condition min. typ. max. unit clock frequency f clk x tal -500ppm 30 +500ppm mhz oscillator block -500ppm 30 +500ppm mhz clock duty cycle t duty 40 50 60 % remarks 1. reccomended accurarcy of clock frequency is 100ppm. 2. required accurarcy of x tal or oscillator block is includeing initial frequency accuracy, the spread of x tal capacityor loading, supply voltage, temperature, and aging etc. (2) reset symbol specification min. typ. max. unit tr reset width 2 s hw reset timing resetb tr
data sheet s16685ej2v0ds 21 pd720122 2.6.2 ac characteristics of biu block with function 1 selected (1) cpu bus read operation symbol parameter min. typ. max. unit t1 read cycle time 91 ns t2 address setup time (rdb ) 5 ns t3 chip select setup time (rdb ) 5 ns t4 buffer direction change time (rdb ) ? 14 ns t5 output data delay time (rdb ) ? 57 ns t6 read command width 57 ns t7 chip select hold time (rdb ) 5 ns t8 address hold time (rdb ) 5 ns t9 rdb inactive time 34 ns t10 output data hold time (rdb ) 4 ? ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). cpu bus read timing rdb wrb a7 to a1 d15 to d0 csb valid valid t 3 t 5 t 6 t 10 t 8 t 7 high level invalid t 4 high level t 1 t 9 t 2
data sheet s16685ej2v0ds 22 pd720122 (2) cpu bus write operation symbol parameter min. typ. max. unit t11 write cycle time 68 ns t12 address setup time (wrb ) 5 ns t13 chip select setup time (wrb ) 5 ns t14 write command width 34 ns t15 address hold time (wrb ) 5 ns t16 chip select hold time (wrb ) 5 ns t17 wrb inactive time 34 ns t18 input data setup time 10 ns t19 input data hold time 0 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). cpu bus write timing w rb rdb a7 to a1 d15 to d0 csb valid t 12 t 13 t 14 t 19 t 15 t 16 t 18 high level t 11 t 17 valid
data sheet s16685ej2v0ds 23 pd720122 (3) cpu bus rdb vs. wrb timing symbol parameter min. typ. max. unit t20 wrb vs. rdb inactive time 34 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). cpu bus read vs. write change timing wrb rdb csb low level t 20
data sheet s16685ej2v0ds 24 pd720122 (4) cpu bus dma transfer (a) cpu bus dma single mode read transfer timing symbol parameter min. typ. max. unit t21 dma request acknowledge setup time (rdb ) 0 ns t22 dma request off time (ep1_dackb ) ? 54 ns t23 dma single mode read transfer cycle time 91 ns t24 read command width 57 ns t25 read command inactive time 34 ns t26 read data delay time (rdb ) ? 57 ns t27 buffer direction change time (rdb ) ? 14 ns t28 read data hold time (rdb ) 4 ? ns t29 ep1_tcb setup time (rdb ) 0 note ns t30 ep1_tcb hold time (rdb ) 17 ns t31 ep1_stopb delay time (rdb ) ? 15 ns t32 ep1_stopb off delay time (rdb ) 3 ? ns t33 dma request acknowledge hold time (rdb ) 0 ns t34 undefined ?? ns note can be input after previous rdb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep1_drqb ep1_tcb d15 to d0 rdb ep1_dackb t 22 t 33 t 24 t 25 t 26 t 28 high level ep1_stopb high level ep1_stopb is not asserted in the case of a full packet. n cycle n ? ? ? ? 1 cycle 1 cycle t 21 t 23 t 27 t 31 t 32
data sheet s16685ej2v0ds 25 pd720122 (start timing) ep1_dackb rdb ep1_drqb ep1_tcb d15 to d0 high level t 21 t 24 t 25 t 26 t 28 t 27 t 33 t 22 t 23 valid valid ep1_stopb high level (end timing) ep1_dackb rdb ep1_drqb t 22 ep1_tcb high level ep1_stopb t 33 high level d15 to d0 t 31 t 32 ep1_stopb is not asserted in the case of a full packet. last ? 1 last valid valid
data sheet s16685ej2v0ds 26 pd720122 (tcb timing) ep1_dackb ep1_drqb ep1_tcb t 22 t 29 t 21 t 30 rdb
data sheet s16685ej2v0ds 27 pd720122 (b) cpu bus dma single mode write transfer symbol parameter min. typ. max. unit t35 dma request acknowledge setup time (wrb ) 0 ns t36 dma request off time (ep2_dackb ) ? 54 ns t37 dma single mode write transfer cycle time 88 ns t38 write command width 54 ns t39 write command inactive time 34 ns t40 write data setup time (wrb ) 10 ns t41 write data hold time (wrb ) 0 ns t42 ep2_tcb setup time (wrb ) 0 note ns t43 ep2_tcb hold time (wrb ) 17 ns t44 dma request acknowledge hold time (wrb ) 0 ns note can be input after immediately previous wrb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep2_drqb ep2_tcb d15 to d0 wrb ep2_dackb t 36 t 38 t 37 t 39 t 40 t 41 high level n cycle n ? ? ? ? 1 cycle 1 cycle t 35 t 44 t 40 t 41 t 44
data sheet s16685ej2v0ds 28 pd720122 (start timing) ep2_dackb wrb ep2_drqb high level t 35 t 38 ep2_tcb t 39 d15 to d0 t 40 t 41 t 44 t 36 t 37 valid valid (end timing) ep2_dackb wrb ep2_drqb t 36 ep2_tcb high level t 44 d15 to d0 valid valid last ? 1 last t 40 t 41
data sheet s16685ej2v0ds 29 pd720122 (tcb timing) ep2_dackb ep2_drqb ep2_tcb t 36 t 42 wrb t 35 t 43
data sheet s16685ej2v0ds 30 pd720122 (c) cpu bus dma demand read transfer timing symbol parameter min. typ. max. unit t45 dma request acknowledge setup time (rdb ) 0 ns t46 dma demand mode read transfer cycle time 91 ns t47 read command width 57 ns t48 read command inactive time 34 ns t49 read data delay time (rdb ) ? 57 ns t50 buffer direction change time (rdb ) ? 14 ns t51 read data hold time (rdb ) 4 ? ns t52 ep1_tcb setup time (rdb ) 0 note ns t53 ep1_tcb hold time (rdb ) 17 ns t54 ep1_stopb delay time (rdb ) ? 15 ns t55 ep1_stopb delay time (rdb ) 3 ? ns t56 dma request off time (rdb ) ? 59 ns t57 dma request acknowledge hold time (rdb ) 0 ns t69 dma request off time (ep1_dackb ) ? 38 ns t71 dma request off time (ep1_dackb ) 1 cycle transfer ? 38 ns t72 dma request on time (ep1_dackb ) ? 88 ns t74 dma request off time (rdb ) ? 60 ns note can be input after immediately previous rdb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep1_drqb ep1_tcb d15 to d0 rdb ep1_dackb n cycle n ? ? ? ? 1 cycle 1 cycle t 46 t 47 t 48 t 49 t 51 t 56 high level t 45 t 50 t 57 ep1_stopb high level t 54 t 55 ep1_stopb is not asserted in the case of a full packet.
data sheet s16685ej2v0ds 31 pd720122 (start timing) ep1_dackb rdb ep1_drqb high level t 45 t 47 ep1_tcb t 48 d15 to d0 valid valid t 50 t 51 t 49 (end timing) ep1_dackb rdb ep1_drqb t 56 ep1_tcb high level ep1_stopb t 57 high level d15 to d0 valid valid last ? 1 last t 54 t 55 ep1_stopb is not asserted in the case of a full packet.
data sheet s16685ej2v0ds 32 pd720122 (tcb timing) rdb ep1_tcb t 74 t 53 ep1_drqb ep1_dackb t 52 (retransmission timing) ep1_dackb rdb ep1_drqb t 56 ep1_tcb high level ep1_stopb t 69 high level d15 to d0 valid valid last ? 1 last t 54 t 55 ep1_stopb is not asserted in the case of a full packet. dma transfer retry timing if ep1_dackb is deasserted without rdb access after ep1_drqb has been deasserted, ep1_drqb is asserted again. t 72
data sheet s16685ej2v0ds 33 pd720122 (if ep1_tcb is input when retransmission is executed) rdb ep1_tcb t 52 t 53 ep1_drqb ep1_dackb t 69 t 45 (one-cycle transfer) ep1_dackb rdb ep1_drqb high level t 45 t 47 ep1_tcb d15 to d0 valid t 50 t 51 t 49 t 71 ep1_stopb t 54 t 55
data sheet s16685ej2v0ds 34 pd720122 (d) cpu bus dma demand write transfer timing symbol parameter min. typ. max. unit t58 dma request acknowledge setup time (wrb ) 0 ns t59 dma demand mode write transfer cycle time 72 ns t60 write command width 38 ns t61 write command inactive time 34 ns t62 write data setup time (wrb ) 10 ns t63 write data hold time (wrb ) 0 ns t64 ep2_tcb setup time (wrb ) 0 note ns t65 ep2_tcb hold time (wrb ) 17 ns t66 dma request off time (wrb ) ? 60 ns t67 dma request acknowledge hold time (wrb ) 0 ns t70 dma request off time (ep2_dackb ) ? 38 ns t73 dma request on time (ep2_dackb ) ? 88 ns t75 dma request off time (wrb ) ? 60 ns note can be input after immediately previous wrb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep2_drqb ep2_tcb d15 to d0 wrb ep2_dackb n cycle n ? ? ? ? 1 cycle 1 cycle t 59 t 60 t 61 t 62 t 63 t 66 high level t 58 t 67
data sheet s16685ej2v0ds 35 pd720122 (start timing) ep2_dackb wrb ep2_drqb ep2_tcb d15 to d0 high level t 58 t 60 t 61 valid valid t 62 t 63 (end timing) ep2_dackb w rb ep2_drqb ep2_tcb last ? 1 last d15 to d0 valid valid t 62 t 63 t 66 t 67
data sheet s16685ej2v0ds 36 pd720122 (tcb timing) wrb ep2_tcb t 75 t 65 ep2_drqb ep2_dackb t 64 (retransmission timing) ep2_dackb w rb ep2_drqb t 66 ep2_tcb high level t 70 d15 to d0 valid valid last ? 1 last dma transfer retry timing if ep2_dackb is deasserted without wrb access after ep2_drqb has been deasserted, ep2_drqb is asserted again. t 73 t 62 t 63
data sheet s16685ej2v0ds 37 pd720122 (if ep1_tcb is input when retransmission is executed) wrb ep2_tcb t 64 t 65 ep2_drqb ep2_dackb t 70 t 58
data sheet s16685ej2v0ds 38 pd720122 (a) cpu bus dma read transfer vs. write transfer timing symbol parameter min. typ. max. unit t68 rdb vs. wrb command inactive time 34 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). ep1_dackb rdb ep1_drqb ep2_dackb wrb ep2_drqb t 45 t 57 t 58 t 68 low level low level
data sheet s16685ej2v0ds 39 pd720122 2.6.3 ac characteristics of biu block with function 2 or 3 selected (1) cpu bus read operation symbol parameter min. typ. max. unit tb1 read cycle time 86 ns tb2 address setup time (ale ) 10 ns tb3 chip select setup time (ale ) 17 ns tb4 read command delay time (ale ) 7 ns tb5 output data delay time (rdb ) ? 57 ns tb6 read command width 57 ns tb7 output data hold time (rdb ) 4 ? ns tb8 chip select hold time (rdb ) 5 ns tb9 ale width 10 ns tb10 address hold time (ale ) 0 ns tb11 chip select setup time (rdb ) 5 ns tb12 buffer direction change time (rdb ) ? 14 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). cpu bus read timing rdb ad7 to ad0 note d15 to d8 csb addres valid tb 7 tb 6 tb 5 ale data valid tb 2 tb 4 tb 8 addres valid tb 1 tb 9 tb 11 tb 12 tb 10 data invalid tb 3 note d7 to d0 for function 2
data sheet s16685ej2v0ds 40 pd720122 (2) cpu bus write operation symbol parameter min. typ. max. unit tb13 write cycle time 58 ns tb14 address setup time (ale ) 17 ns tb15 chip select setup time (ale ) 17 ns tb16 write command delay time (ale ) 7 ns tb17 input data setup time (wrb ) 10 ns tb18 input data hold time (wrb ) 0 ns tb19 write command width 34 ns tb20 chip select hold time (wrb ) 0 ns tb21 chip select setup time (wrb ) 5 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). cpu bus write timing wrb ad7 to ad0 note d15 to d8 csb address valid tb 18 tb 19 ale data valid tb 2 tb 16 tb 20 address valid tb 13 tb 17 tb 10 tb 21 tb 15 tb 9 note d7 to d0 for function 2
data sheet s16685ej2v0ds 41 pd720122 2.6.4 external local bus (1) external local bus 16-bit mode (a) external local bus 16-bit mode dma single mode read transfer timing symbol parameter min. typ. max. unit l16t21 dma request acknowledge setup time (ep1_rdb ) 0 ns l16t22 dma request off time 1 (ep1_dackb ) ? 54 ns l16t23 dma single mode read transfer cycle time 91 ns l16t24 read command width 57 ns l16t25 read command inactive time 34 ns l16t26 read data delay time (ep1_rdb ) ? 57 ns l16t27 buffer direction change time (ep1_rdb ) ? 14 ns l16t28 read data hold time (ep1_rdb ) 4 ? ns l16t29 ep1_tcb setup time (ep1_rdb ) 0 note ns l16t30 ep1_tcb hold time (ep1_rdb ) 17 ns l16t31 ep1_stopb delay time (ep1_rdb ) ? 15 ns l16t32 ep1_stopb delay time (ep1_rdb ) 3 ? ns l16t33 dma request acknowledge hold time (ep1_rdb ) 0 ns l16t34 undefined ?? ns note can be input after previous ep1_rdb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf).
data sheet s16685ej2v0ds 42 pd720122 (overall) ep1_drqb ep1_tcb ld15 to ld0 ep1_rdb ep1_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l16t 22 l16t 23 l16t 24 l16t 25 l16t 26 l16t 28 high level ep1_stopb high level ep1_stopb is not asserted in the case of a full packet. l16t 21 l16t 33 l16t 27 l16t 31 l16t 32 (start timing) ep1_dackb ep1_rdb ep1_drqb ep1_tcb ld15 to ld0 high level l16t 21 l16t 24 l16t 25 valid valid l16t 26 l16t 28 l16t 27 l16t 33 l16t 22 l16t 23
data sheet s16685ej2v0ds 43 pd720122 (end timing) l16t 22 high level l16t 33 high level valid valid last ? 1 last l16t 31 l16t 32 ep1_stopb is not asserted in the case of a full packet. ep1_dackb ep1_rdb ep1_drqb ep1_tcb ep1_stopb ld15 to ld0 (tcb timing) ep1_dackb ep1_drqb ep1_rdb ep1_tcb l16t 22 l16t 21 l16t 29 l16t 30
data sheet s16685ej2v0ds 44 pd720122 (a) external local bus 16-bit mode dma single mode write transfer symbol parameter min. typ. max. unit l16t35 dma request acknowledge setup time (ep2_wrb ) 0 ns l16t36 dma request off time 1 (ep2_dackb ) ? 54 ns l16t37 dma single mode write transfer cycle time 88 ns l16t38 write command width 54 ns l16t39 write command inactive time 34 ns l16t40 write data setup time (ep2_wrb ) 10 ns l16t41 write data hold time (ep2_wrb ) 0 ns l16t42 ep2_tcb setup time (ep2_wrb ) 0 note ns l16t43 ep2_tcb hold time (ep2_wrb ) 17 ns l16t44 dma request acknowledge hold time (ep2_wrb ) 0 ns note can be input after previous ep2_wrb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep2_drqb ep2_tcb ld15 to ld0 ep2_wrb ep2_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l16t 36 l16t 38 l16t 37 l16t 39 l16t 40 l16t 41 high level l16t 35 l16t 44 l16t 41 l16t 40
data sheet s16685ej2v0ds 45 pd720122 (start timing) ep2_dackb ep2_wrb ep2_drqb ep2_tcb ld15 to ld0 high level l16t 35 l16t 38 l16t 39 valid valid l16t 40 l16t 41 l16t 44 l16t 36 l16t 37 (end timing) ep2_dackb ep2_wrb ep2_drqb l16t 36 ep2_tcb high level l16t 44 ld15 to ld0 valid valid last ? 1 last l16t 40 l16t 41
data sheet s16685ej2v0ds 46 pd720122 (tcb timing) ep2_dackb ep2_drqb ep2_wrb l16t 36 l16t 35 ep2_tcb l16t 43 l16t 42
data sheet s16685ej2v0ds 47 pd720122 (c) external local bus 16-bit mode dma demand read transfer timing symbol parameter min. typ. max. unit l16t45 dma request acknowledge setup time (ep1_rdb ) 0 ns l16t46 dma demand mode read transfer cycle time 91 ns l16t47 read command width 57 ns l16t48 read command inactive time 34 ns l16t49 read data delay time (ep1_rdb ) ? 57 ns l16t50 buffer direction change time (ep1_rdb ) ? 14 ns l16t51 read data hold time (ep1_rdb ) 4 ? ns l16t52 ep1_tcb setup time (ep1_rdb ) 0 note ns l16t53 ep1_tcb hold time (ep1_rdb ) 17 ns l16t54 ep1_stopb delay time (ep1_rdb ) ? 15 ns l16t55 ep1_stopb delay time (ep1_rdb ) 3 ? ns l16t56 dma request off time (ep1_rdb ) ? 59 ns l16t57 dma request acknowledge hold time (ep1_rdb ) 0 ns l16t69 dma request off time (ep1_dackb ) ? 38 ns l16t71 dma request off time (ep1_dackb ) 1 cycle transfer ? 38 ns l16t72 dma request on time (ep1_dackb ) ? 88 ns l16t74 dma request off time (ep1_rdb ) ? 60 ns note can be input after immediately previous ep1_rdb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf).
data sheet s16685ej2v0ds 48 pd720122 (overall) ep1_drqb ep1_tcb ld15 to ld0 ep1_rdb ep1_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l16t 46 l16t 47 l16t 48 l16t 49 l16t 51 l16t 56 high level ep1_stopb high level l16t 57 l16t 54 l16t 55 ep1_stopb is not asserted in the case of a full packet. l16t 45 l16t 50 (start timing) ep1_dackb ep1_rdb ep1_drqb high level l16t 45 l16t 47 ep1_tcb l16t 48 ld15 to ld0 valid valid l16t 50 l16t 51 l16t 49 l16t 46
data sheet s16685ej2v0ds 49 pd720122 (end timing) ep1_dackb ep1_rdb ep1_drqb l16t 56 ep1_tcb high level ep1_stopb l16t 57 high level ld15 to ld0 valid valid last ? 1 last l16t 54 l16t 55 ep1_stopb is not asserted in the case of a full packet. (tcb timing) ep1_rdb ep1_tcb l16t 53 ep1_drqb ep1_dackb l16t 74 l16t 52
data sheet s16685ej2v0ds 50 pd720122 (retransmission timing) ep1_dackb ep1_rdb ep1_drqb l16t 56 ep1_tcb high level ep1_stopb l16t 69 high level ld15 to ld0 valid valid last ? 1 last l16t 54 l16t 55 ep1_stopb is not asserted in the case of a full packet. dma transfer retry timing if ep1_dackb is deasserted without rdb access after ep1_drqb has been deasserted, ep1_drqb is asserted again. however, note that the retry operation cannot be performed in the 8-bit mode. l16t 72 (if ep1_tcb is input when retransmission is executed) ep1_rdb ep1_tcb l16t 53 ep1_drqb ep1_dackb l16t 69 l16t 52 l16t 45
data sheet s16685ej2v0ds 51 pd720122 (one-cycle transfer) ep1_dackb ep1_rdb ep1_drqb high level l16t 45 l16t 47 ep1_tcb ld15 to ld0 valid l16t 50 l16t 51 l16t 49 l16t 71 ep1_stopb l16t 54 l16t 55
data sheet s16685ej2v0ds 52 pd720122 (d) external local bus 16-bit mode dma demand write transfer timing symbol parameter min. typ. max. unit l16t58 dma request acknowledge setup time (ep2_wrb ) 0 ns l16t59 dma demand mode write transfer cycle time 72 ns l16t60 write command width 38 ns l16t61 write command inactive time 34 ns l16t62 write data setup time (ep2_wrb ) 10 ns l16t63 write data hold time (ep2_wrb ) 0 ns l16t64 ep2_tcb setup time (ep2_wrb ) 0 note ns l16t65 ep2_tcb hold time (ep2_wrb ) 17 ns l16t66 dma request off time (ep2_wrb ) ? 60 ns l16t67 dma request acknowledge hold time (ep2_wrb ) 0 ns l16t70 dma request off time (ep2_dackb ) ? 38 ns l16t73 dma request on time (ep2_dackb ) ? 88 ns l16t75 dma request off time (ep2_wrb ) ? 60 ns note can be input after previous ep2_wrb . remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep2_drqb ep2_tcb ld15 to ld0 ep2_wrb ep2_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l16t 59 l16t 60 l16t 61 l16t 62 l16t 63 l16t 66 high level l16t 58 l16t 67
data sheet s16685ej2v0ds 53 pd720122 (start timing) ep2_dackb ep2_wrb ep2_drqb high level l16t 58 l16t 60 ep2_tcb l16t 61 ld15 to ld0 valid valid l16t 62 l16t 63 l16t 59 (end timing) ep2_dackb ep2_wrb ep2_drqb ep2_tcb last ? 1 last ld15 to ld0 valid valid l16t 62 l16t 63 l16t 66 l16t 67 high level
data sheet s16685ej2v0ds 54 pd720122 (tcb timing) ep2_wrb ep2_tcb l16t 75 l16t 65 ep2_drqb ep2_dackb l16t 64 (retransmission timing) ep2_dackb ep2_wrb ep2_drqb l16t 66 ep2_tcb high level l16t 70 ld15 to ld0 valid valid last ? 1 last dma transfer retry timing if ep2_dackb is deasserted without rdb access after ep2_drqb has been deasserted, ep2_drqb is asserted again. however, note that the retry operation cannot be performed in the 8-bit mode. l16t 73 l16t 62 l16t 63
data sheet s16685ej2v0ds 55 pd720122 (if ep1_tcb is input when retransmission is executed) ep2_wrb ep2_tcb l16t 64 l16t 65 ep2_drqb ep2_dackb l16t 70 l16t 58 (e) external local bus 16-bit mode dma ep1_read transfer vs. ep2_write transfer timing symbol parameter min. typ. max. unit l16t68 ep1_rdb vs. ep2_wrb command inactive time 34 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). ep1_dackb ep1_rdb ep1_drqb ep2_dackb ep2_wrb ep2_drqb l16t 45 l16t 57 l16t 58 l16t 68 low level low level
data sheet s16685ej2v0ds 56 pd720122 (2) external local bus 8-bit mode (a) external local bus 8-bit mode dma single mode read transfer timing symbol parameter min. typ. max. unit l8t21 dma request acknowledge setup time (ep1_rdb ) 0 ns l8t22 dma request off time 1 (ep1_dackb ) ? 10 ns l8t23 dma single mode read transfer cycle time 91 ns l8t24 read command width 57 ns l8t25 read command inactive time 34 ns l8t26 read data delay time (ep1_rdb ) ? 57 ns l8t27 buffer direction change time (ep1_rdb ) ? 14 ns l8t28 read data hold time (ep1_rdb ) 4 ? ns l8t31 ep1_stopb delay time (ep1_rdb ) ? 15 ns l8t32 ep1_stopb delay time (ep1_rdb ) 3 ? ns l8t33 dma request acknowledge hold time (ep1_rdb ) 0 ns l8t34 undefined ?? ns remarks 1. use of ep1_tcb is prohibited in the 8-bit external local bus mode. clamp this signal to the inactive status. 2. ld15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep1_drqb ep1_tcb ld7 to ld0 ep1_rdb ep1_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l8t 22 l8t 23 l8t 24 l8t 25 l8t 26 l8t 28 high level ep1_stopb high level ep1_stopb is not asserted in the case of a full packet. l8t 21 l8t 27 l8t 31 l8t 32 l8t 33
data sheet s16685ej2v0ds 57 pd720122 (start timing) ep1_dackb ep1_rdb ep1_drqb ep1_tcb ld7 to ld0 valid high level l8t 21 l8t 24 l8t 25 valid l8t 26 l8t 28 l8t 27 l8t 33 l8t 22 l8t 23 (end timing) ep1_dackb ep1_rdb ep1_drqb l8t 22 ep1_tcb high level ep1_stopb l8t 33 high level ld7 to ld0 valid valid last ? 1 last l8t 31 l8t 32 ep1_stopb is not asserted in the case of a full packet.
data sheet s16685ej2v0ds 58 pd720122 (b) external local bus 8-bit mode dma single mode write transfer symbol parameter min. typ. max. unit l8t35 dma request acknowledge setup time (ep2_wrb ) 0 ns l8t36 dma request off time 1 (ep2_dackb ) ? 54 note ns l8t37 dma single mode write transfer cycle time 88 ns l8t38 write command width 54 ns l8t39 write command inactive time 34 ns l8t40 write data setup time (ep2_wrb ) 10 ns l8t41 write data hold time (ep2_wrb ) 0 ns l8t44 dma request acknowledge hold time (ep2_wrb ) 0 ns remarks 1. use of ep1_tcb is prohibited in the 8-bit external local bus mode. clamp this signal to the inactive status. 2. ld15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). note the difference in specifications when compared with l8t22 is that biu processing is performed for ep1 and that epc2 processing is performed for ep2. (overall) ep2_drqb ep2_tcb ld7 to ld0 ep2_wrb ep2_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l8t 36 l8t 38 l8t 44 l8t 39 l8t 40 l8t 41 high level l8t 35 l8t 37 l8t 44 l8t 40 l8t 41
data sheet s16685ej2v0ds 59 pd720122 (start timing) ep2_dackb ep2_wrb ep2_drqb ep2_tcb ld7 to ld0 high level l8t 35 l8t 38 l8t 39 valid valid l8t 40 l8t 41 l8t 44 l8t 36 l8t 37 (end timing) ep2_dackb ep2_wrb ep2_drqb l8t 36 ep2_tcb high level l8t 44 ld7 to ld0 valid valid last ? 1 last l8t 40 l8t 41
data sheet s16685ej2v0ds 60 pd720122 (c) external local bus 8-bit mode dma demand read transfer timing symbol parameter min. typ. max. unit l8t45 dma request acknowledge setup time (ep1_rdb ) 0 ns l8t46 dma demand mode read transfer cycle time 90 ns l8t47 read command width 56 ns l8t48 read command inactive time 34 ns l8t49 read data delay time (ep1_rdb ) ? 56 ns l8t50 buffer direction change time (ep1_rdb ) ? 14 ns l8t51 read data hold time (ep1_rdb ) 4 ? ns l8t54 ep1_stopb delay time (ep1_rdb ) ? 15 ns l8t55 ep1_stopb delay time (ep1_rdb ) 3 ? ns l8t56 dma request off time (ep1_rdb ) ? 60 ns l8t57 dma request acknowledge hold time (ep1_rdb ) 0 ns remarks 1. use of ep1_tcb is prohibited in the 8-bit external local bus mode. clamp this signal to the inactive status. 2. ld15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep1_drqb ep1_tcb ld7 to ld0 ep1_rdb ep1_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l8t 46 l8t 47 l8t 48 l8t 49 l8t 51 l8t 56 high level ep1_stopb high level l8t 54 l8t 55 l8t 57 ep1_stopb is not asserted in the case of a full packet. l8t 50 l8t 45
data sheet s16685ej2v0ds 61 pd720122 (start timing) ep1_dackb ep1_rdb ep1_drqb high level l8t 45 l8t 47 ep1_tcb l8t 48 ld7 to ld0 valid valid l8t 50 l8t 51 l8t 49 (end timing) ep1_dackb ep1_rdb ep1_drqb l8t 56 ep1_tcb high level ep1_stopb l8t 57 high level ld7 to ld0 valid valid last ? 1 last l8t 54 l8t 55 ep1_stopb is not asserted in the case of a full packet.
data sheet s16685ej2v0ds 62 pd720122 (d) external local bus 8-bit mode dma demand write transfer timing symbol parameter min. typ. max. unit l8t58 dma request acknowledge setup time (ep2_wrb ) 0 ns l8t59 dma demand mode write transfer cycle time 72 ns l8t60 write command width 38 ns l8t61 write command inactive time 34 ns l8t62 write data setup time (ep2_wrb ) 10 ns l8t63 write data hold time (ep2_wrb ) 0 ns l8t66 dma request off time (ep2_wrb ) ? 60 ns l8t67 dma request acknowledge hold time (ep2_wrb ) 0 ns remarks 1. use of ep1_tcb is prohibited in the 8-bit external local bus mode. clamp this signal to the inactive status. 2. ld15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). (overall) ep2_drqb ep2_tcb ld7 to ld0 ep2_wrb ep2_dackb n cycle n ? ? ? ? 1 cycle 1 cycle l8t 59 l8t 60 l8t 61 l8t 62 l8t 63 l8t 66 high level l8t 67 l8t 62 l8t 63 l8t 58
data sheet s16685ej2v0ds 63 pd720122 (start timing) ep2_dackb ep2_wrb ep2_drqb high level l8t 58 l8t 60 ep2_tcb l8t 61 ld7 to ld0 valid valid l8t 62 l8t 63 l8t 59 (end timing) ep2_dackb ep2_wrb ep2_drqb ep2_tcb last ? 1 last ld7 to ld0 valid valid l8t 62 l8t 63 l8t 66 l8t 67
data sheet s16685ej2v0ds 64 pd720122 (e) external local bus 8-bit mode dma ep1_read transfer vs. ep2_write transfer timing symbol parameter min. typ. max. unit l8t68 ep1_rdb vs. ep2_wrb command inactive time 34 ns remark it is assumed that the external pin capacitance is 15 pf (data bus = 50 pf). ep1_dackb ep1_rdb ep1_drqb l8t 45 l8t 57 ep2_dackb ep2_wrb ep2_drqb l8t 58 l8t 68 low level low level
data sheet s16685ej2v0ds 65 pd720122 2.6.5 usb interface timing parameter symbol conditions min. max. unit full-speed source electrical characteristics rise time t fr c l = 50 pf, r s = 36 ? 420ns fall time t ff c l = 50 pf, r s = 36 ? 420ns differential rise and fall time matching t frfm (t fr /t ff ) 90 111.11 % full-speed data rate for hubs and devices that are high-speed capable t fdraths average bit rate 11.9940 12.0060 mb/s frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4.0 3.5 4.0 ns ns source jitter for differential transition to se0 transition t fdeop ? 2 5ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 18.5 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns high-speed source electrical characteristics rise time (10% to 90%) t hsr 500 ps fall time (10% to 90%) t hsf 500 ps driver waveform requirements see figure 2-6 high-speed data rate t hsdrat 479.760 480.240 mb/s microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high-speed bit times data source jitter see figure 2-6 . receiver jitter tolerance see figure 2-4 .
data sheet s16685ej2v0ds 66 pd720122 parameter symbol conditions min. max. unit device event timing time from internal power good to device pulling d+/d ? beyond v ihz (min.) (signaling attach) t sigatt 100 ms debounce interval provided by usb system software after attach t attdb 100 ms inter-packet delay (for low-/full-speed) t ipd 2 bit times inter-packet delay for device response w/detachable cable for low-/full-speed t rspipd1 6.5 bit times high-speed detection start time from suspend t sca 2.5 s sample time for suspend vs. reset t csr 100 875 s power down under suspend t sus 10 ms suspend set time (spndout) t ssp 0 ? suspend clear time (rsumout) t csp 0 ? reversion time from suspend to high-speed t rhs 1.333 s suspend setup time (rsumin) t srw 0 ? rsumin active pulse width t rwp 115ms drive chirp k width t cko 1ms finish chirp k assertion t fca 7ms start sequencing chirp k-j-k-j-k-j t ssc 100 s finish sequencing chirp k-j t fsc ? 500 ? 100 s detect sequencing chirp k-j width t csi 2.5 s sample time for sequencing chirp t scs 1.0 2.5 ms reversion time to high-speed t rha 500 s high-speed detection start time t hds 2.5 3000 s reset completed time t drs 10 ms
data sheet s16685ej2v0ds 67 pd720122 figure 2-6. transmit waveform for transceiver at d+/d ? ? ? ? 0 v differential +400 mv differential ? 400 mv differential unit interval level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 0% 100% figure 2-7. transmitter measurement fixtures vbus d+ d ? gnd 15.8 ? + to 50- ? input of a high-speed differential oscilloscope, or 50- ? output of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s16685ej2v0ds 68 pd720122 (1) power-on and connection events figure 2-8. power-on and connection event timing ? t1 100 ms t sigatt 4.01 v d+ or d ? 100 ms t attdb hub port power-on hub port power ok attach detected ? t4 ? t5 usb system software reads device speed v ih (min) 10 ms reset recovery time ? t6 v bus v ih (2) usb signals figure 2-9. usb differential data jitter for full-speed t period differential data lines crossover points paired transitions n * t period + t xdj2 consecutive transitions n * t period + t xdj1
data sheet s16685ej2v0ds 69 pd720122 figure 2-10. usb differential-to-eop transition skew and eop width for full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt t leopt receiver eop width: t feopr , t leopr diff. data-to- se0 skew n * t period + t xdeop
data sheet s16685ej2v0ds 70 pd720122 figure 2-11. usb receiver jitter tolerance for full-speed differential data lines paired transitions n * t period + t xjr2 t period consecutive transitions n * t period + t xjr1 t xjr t xjr1 t xjr2 (3) usb connection sequence on usb1.1 bus the phy core implemented on the pd720122 automatically determines the up port. check the sp_mode bit (sp_mode) of the int status 2 register after an epc2_stg bus reset interrupt has occurred to determine whether the usb is connected to fs or hs. figure 2-12. usb connection sequence on usb 1.1 bus t hds t sca t cko t cki t scs t fca t drs chirp k device out reversion to full-speed mode fs j fs j pull-up is active. t 0 high usb bus usbrst spmode
data sheet s16685ej2v0ds 71 pd720122 (4) usb connection sequence on usb 2.0 bus figure 2-13. usb connection sequence on usb 2.0 bus t hds t sca t cko t cki t scs t fca chirp k device out reversion to high-speed mode fs j pull-up is active. t 0 usb bus usbrst spmode t ssc t cso t csi t rha t fsc chirp state from host/hub reset complete kj kjkjkj (5) bus reset sequence (1) the bus reset sequence when connected to a usb 1.1 bus is shown below. figure 2-14. bus reset sequence (1) t spd t sca t cko t cki t scs t drs chirp k device out reversion to full-speed mode fs j pull-up is inactive. t 0 usb bus usbrst spmode t fca t csr high-speed packet
data sheet s16685ej2v0ds 72 pd720122 (6) bus reset sequence (2) the bus reset sequence when connected to a usb 2.0 bus is shown below. figure 2-15. bus reset sequence (2) t spd t csr t cko t cki t scs t fca chirp k device out reversion to high-speed mode pull-up is inactive t 0 usb bus usbrst spmode t ssc t cso t csi t rha t fsc chirp state from host/hub reset complete kjkjkjkj hi g h-speed packet t sca reversion to full-speed mode
data sheet s16685ej2v0ds 73 pd720122 (7) usb reset from suspend state (1) figure 2-16. usb reset from suspend state (1) t sca t cko t cki t scs t fca t drs chirp k device out fs j fs j pull-up is active. t 0 usb bus usb_rst spmode (8) usb reset from suspend state (2) figure 2-17. usb reset from suspend state (2) t cko t cki t scs t fca chirp k device out reversion to hi g h-speed mode pull-up is inactive. t 0 usb bus usbrst spmode t ssc t cso t csi t rha t fsc chirp state from host/hub reset complete kjkjkjkj t sca fs j
data sheet s16685ej2v0ds 74 pd720122 (9) suspend and resume on usb1.1 bus figure 2-18. suspend and resume on usb 1.1 bus usb bus suspend spmode fs j fs j fs k fs eop t spd t sus t ssp t csp current source and pll, etc. are disabled. note time re q uired to relock pll and stabilize oscillator. high spndout rsumout
data sheet s16685ej2v0ds 75 pd720122 (10) suspend and resume on usb2.0 bus figure 2-19. suspend and resume on usb 2.0 bus usb bus suspend spmode fs j fs k high-speed packet t spd t sus t ssp t csp current source and pll, etc. are disabled. note time re q uired to relock pll and stabilize oscillator. low spndout rsumout t csr reversion to full-speed mode t rhs high-speed packet reversion to high-speed mode t 0 (11) remote wakeup on usb1.1 figure 2-20. remote wakeup on usb 1.1 usb bus suspend spmode fs j fs k t spd t sus t ssp current source and pll, etc. are disabled. high spndout rsumout fs j fs eop t rwp t srw rsumin
data sheet s16685ej2v0ds 76 pd720122 (12) remote wakeup on usb2.0 figure 2-21. remote wakeup on usb 2.0 usb bus suspend speedmode fs j fs k t spd t sus t ssp current source and pll, etc. are disabled. low spndout rsumout t 0 t rwp t srw rsumin high-speed packet reversion to full-speed mode t rhs reversion to high-speed mode t csr high-speed packet
data sheet s16685ej2v0ds 77 pd720122 3. package drawing 75 76 50 100 1 26 25 51 s 100-pin plastic tqfp (fine pitch) (14x14) item millimeters b 14.0 0.2 d 16.0 0.2 f 1.0 g 1.0 a 16.0 0.2 c 14.0 0.2 h 0.22 0.05 i 0.08 j k note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 1.0 0.2 0.5 (t.p.) a r detail of lead end s m hi g f b c d l 0.5 n 0.08 p 1.0 q 0.1 0.05 p100gc-50-9eu m 0.17 + 0.03 ? 0.07 s 1.1 0.1 t 0.25 u 0.6 0.15 r3 + 4 ? 3 k j p q l u t m s n
data sheet s16685ej2v0ds 78 pd720122 b s a d e s wa s wb index mark ze a a2 a1 zd 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m y1 s s y s e x bab m ? item dimensions d e w a a1 a2 e b x y y1 zd ze 11.00 0.10 11.00 0.10 0.80 0.08 0.10 0.20 1.10 1.10 0.20 0.35 0.06 1.28 0.10 0.93 p109f1-80-dn2 (unit:mm) 0.50 +0.05 ? 0.10 109-pin plastic fbga (11x11)
data sheet s16685ej2v0ds 79 pd720122 4. recommended soldering conditions the pd720122 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact your nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) ? pd720122gc-9eu : 100-pin plastic tqfp (fine pitch) (14 14) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. ? pd720122f1-gn2 : 109-pin plastic fbga (11 11) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-3 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet s16685ej2v0ds 80 pd720122 [memo]
data sheet s16685ej2v0ds 81 pd720122 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd720122 eeprom is a trademark of nec electronics corporation. usb logo is a trademark of usb implementers forum, inc. the information in this document is current as of june, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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